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ksz9021rl/rn gigabit ethernet transceiver with rgmii support linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com october 2009 m9999-101309-1.1 general description the ksz9021rl is a completely integrated triple speed (10base-t/100base-tx/1000base-t) ethernet physical layer transceiver for transmission and reception of data over standard cat-5 unshiel ded twisted pair (utp) cable. the ksz9021rl provides the reduced gigabit media independent interface (rgmii) for direct connection to rgmii macs in gigabit ethernet processors and switches for data transfer at 10/100/1000mbps speed. the ksz9021rl reduces board cost and simplifies board layout by using on-chip termin ation resistors for the four differential pairs and by integrating a ldo controller to drive a low cost mosfet to supply the 1.2v core. the ksz9021rl provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between ksz9021 i/os and board. micrel linkmd ? tdr-based cable diagnostics permit identification of faulty copper cabling. remote and local loopback functions provide verification of analog and digital data paths. the ksz9021rl is available in a 64-pin, lead-free e-lqfp package, and is offered as the ksz9021rn in the smaller 48-pin qfn package (see ordering information). features ? single-chip 10/100/1000mbps ieee 802.3 compliant ethernet transceiver ? rgmii interface compliant to rgmii version 1.3 ? rgmii i/os with 3.3v/2.5v tolerant and programmable timings to adjust and correct delays on both tx and rx paths ? auto-negotiation to automatically select the highest link up speed (10/100/100mbps) and duplex (half/full) ? on-chip termination resistors for the differential pairs ? on-chip ldo controller to support single 3.3v supply operation ? requires only external fet to generate 1.2v for the core ? jumbo frame support up to 16kb ? 125mhz reference clock output ? programmable led outputs for link, activity and speed ? baseline wander correction ? linkmd ? tdr-based cable diagnostics for identification of faulty copper cabling ? parametric nand tree support for fault detection between chip i/os and board. ? loopback modes for diagnostics ____________________________________________________________________________________________________________ functional diagram
micrel, inc. ksz9021rl/rn october 2009 2 m9999-101309-1.1 more features ? automatic mdi/mdi-x crossover for detection and correction of pair swap at all speeds of operation ? automatic detection and correction of pair swap, pair skew and pair polarity ? mdc/mdio management interface for phy register configuration ? interrupt pin option ? power down and power saving modes ? operating voltages core: 1.2v (external fet or regulator) i/o: 3.3v or 2.5v transceiver: 3.3v ? available packages 64-pin e-lqfp (10mm x 10mm): ksz9021rl 48-pin qfn (7mm x 7mm): ksz9021rn applications ? laser/network printer ? network attached storage (nas) ? network server ? gigabit lan on motherboard (glom) ? broadband gateway ? gigabit soho/smb router ? iptv ? ip set-top box ? game console ? triple-play (data, voice, video) media center ? media converter ordering information part number temp. range package lead finish description ksz9021rl 0c to 70c 64-pin e- lqfp pb-free rgmii, commerci al temperature, 64-e-lqfp ksz9021rli (1) -40c to 85c 64-pin e-lqfp pb-free rg mii, industrial temperature, 64-e-lqfp ksz9021rn 0c to 70c 48-pin qf n pb-free rgmii, commercial temperature, 48-qfn KSZ9021RNI (1) -40c to 85c 48-pin qfn pb-free rg mii, industrial temperature, 48-qfn note: 1. contact factory for lead time.
micrel, inc. ksz9021rl/rn october 2009 3 m9999-101309-1.1 revision history revision date summary of changes 1.0 1/16/09 data sheet created. 1.1 10/13/09 updated current c onsumption in electrical characteristics section. corrected data sheet omission of register 1 bit 8 for 1000base-t extended status information. added the following register bits to provide further power saving during software power down: tri- state all digital i/os (reg. 258.7) , ldo disable (reg. 263.15), low frequency oscilla tor mode (reg. 263.8). added ksz9021rn device and updated entire data sheet accordingly. added 48-pin qfn package information.
micrel, inc. ksz9021rl/rn october 2009 4 m9999-101309-1.1 contents pin configuration ? ksz9021rl ............................................................................................................................... ........... 8 pin description ? ksz9021rl ............................................................................................................................... ............... 9 strapping options ? ksz9021rl ............................................................................................................................... ........ 14 pin configuration ? ksz9021rn ............................................................................................................................... ......... 15 pin description ? ksz9021rn ............................................................................................................................... ............ 16 strapping options ? ksz9021rn ............................................................................................................................... ....... 21 functional overview ............................................................................................................................... ............................ 22 functional description: 10base-t/100base-tx transceiver ......................................................................................... 23 100base-tx transm it............................................................................................................ ........................................... 23 100base-tx receive............................................................................................................. ........................................... 23 scrambler/de-scrambler (100base-tx only)....................................................................................... ............................. 23 10base-t tr ansmit .............................................................................................................. ............................................. 23 10base-t re ceive ............................................................................................................... ............................................. 23 functional description: 1000base-t transceiver .......................................................................................................... 24 analog echo cancel lation circuit ............................................................................................... ...................................... 24 automatic gain control (agc) ................................................................................................... ...................................... 24 analog-to-digital converter (adc) .............................................................................................. ..................................... 24 timing recovery circuit........................................................................................................ ............................................ 25 adaptive eq ualizer............................................................................................................. ............................................... 25 trellis encode r and deco der .................................................................................................... ........................................ 25 functional description: 10/ 100/1000 transceiver features .......................................................................................... 25 auto md i/mdi-x................................................................................................................. ............................................... 25 pair- swap, alignment, and polarity check...................................................................................... ................................ 26 wave shaping, slew rate c ontrol and partia l response........................................................................... ..................... 26 pll clock synthesizer.......................................................................................................... ............................................ 26 auto-negotiation ............................................................................................................................... .................................. 26 rgmii interface ............................................................................................................................... ..................................... 28 rgmii signal defini tion ........................................................................................................ ............................................ 29 rgmii signal diagr am........................................................................................................... ........................................... 29 rgmii in-band status ........................................................................................................... ............................................ 30 mii management (miim) interface ............................................................................................................................... ........ 30 interrupt (int_n) ............................................................................................................................... ................................... 30 led mode ............................................................................................................................... .............................................. 31 single le d mode................................................................................................................ .............................................. 31 tri-color dual led mode ........................................................................................................ .......................................... 31 nand tree support ............................................................................................................................... ............................. 32 power management ............................................................................................................................... ............................. 33
micrel, inc. ksz9021rl/rn october 2009 5 m9999-101309-1.1 power savi ng m ode.............................................................................................................. ............................................ 33 software power down mode ....................................................................................................... ..................................... 33 chip power down mode ........................................................................................................... ........................................ 33 register map ............................................................................................................................... ......................................... 33 register description ............................................................................................................................... ............................ 34 ieee defined r egisters ......................................................................................................... ........................................... 34 vendor specific regist ers ...................................................................................................... .......................................... 41 extended regi sters ............................................................................................................. ............................................. 44 absolute maximum ratings ............................................................................................................................... ................ 46 operating ratings ............................................................................................................................... ................................ 46 electrical characteristic ............................................................................................................................... ...................... 46 timing diagrams ............................................................................................................................... .................................. 48 rgmii timing................................................................................................................... ................................................. 48 auto-negotiati on timi ng ........................................................................................................ ........................................... 49 mdc/mdio timing ................................................................................................................ ........................................... 50 reset timing................................................................................................................... .................................................. 51 reset circuit ............................................................................................................................... ......................................... 51 reference circuits ? led strap-in pins ............................................................................................................................ 52 reference clock ? connection and selection .................................................................................................................. 53 magnetics specification ............................................................................................................................... ...................... 53 package information ............................................................................................................................... ............................ 54
micrel, inc. ksz9021rl/rn october 2009 6 m9999-101309-1.1 list of figures figure 1. ksz9021rl/ rn block diagram.......................................................................................... .................................. 22 figure 2: ksz9021rl/rn 1000base- t block diagram ? single channel .............................................................. ............ 24 figure 3: auto-negot iation flow chart......................................................................................... ........................................ 27 figure 4: ksz9021rl/ rn rgmii interface........................................................................................ .................................. 29 figure 5. rgmii v1.3 specification (fig ure 2 ? multiplexing & timing diagram) ................................................. ............... 48 figure 6. auto-negotiation fa st link pulse (flp) ti ming ....................................................................... ............................ 49 figure 7. mdc/ mdio ti ming..................................................................................................... ........................................... 50 figure 8. re set timing........................................................................................................ ................................................. 51 figure 9. recommend ed reset circuit........................................................................................... ..................................... 51 figure 10. recommended reset circuit for interfacing with cpu/ fpga rese t output ............................................... ...... 52 figure 11. reference circui ts for led st rapping pins.......................................................................... ............................... 52 figure 12. 25mhz crystal / oscilla tor reference cl ock connection .............................................................. ..................... 53
micrel, inc. ksz9021rl/rn october 2009 7 m9999-101309-1.1 list of tables table 1: mdi / mdi-x pin mapping .............................................................................................. ........................................ 25 table 2: auto-neg otiation timers .............................................................................................. .......................................... 28 table 3. rgmii signal defi nition.............................................................................................. ............................................ 29 table 4: rgm ii in-band status ................................................................................................. ........................................... 30 table 5. mii management fr ame format ? for ksz9021r l/rn ....................................................................... .................. 30 table 6: single led m ode ? pin de finition..................................................................................... ..................................... 31 table 7: tri-color dual led mode ? pi n defini tion ............................................................................. ................................. 31 table 8: nand tree test pin order ? fo r ksz9021rl ............................................................................. .......................... 32 table 9: nand tree test pin order ? fo r ksz9021rn ............................................................................. ......................... 32 table 10. rgmii v1.3 specificati on (timing specific s from ta ble 2) ............................................................ ...................... 48 table 11. auto-negotiation fast li nk pulse (flp) ti ming para meters ............................................................ ................... 49 table 12. mdc/mdio timing pa rameters .......................................................................................... ................................. 50 table 13. reset timing parameters ............................................................................................. ....................................... 51 table 14. reference crysta l/clock selection criteria.......................................................................... ................................ 53 table 15. magnetics selection criteria ........................................................................................ ........................................ 53 table 16. qualified singl e port 10/100/1 000 magnetics......................................................................... ............................. 53
micrel, inc. ksz9021rl/rn october 2009 8 m9999-101309-1.1 pin configuration ? ksz9021rl vss avddh vss led2 / phyad1 dvddh led1 / phyad0 dvddl vss txd0 txd1 txd2 txd3 vss dvddl dvddh tx_er gtx_clk agndh_bg iset avddh xi xo avddl_pll ldo_o reset_n clk125_ndo / led_mode dvddl vss dvddl int_n col mdio 64-pin e-lqfp (top view)
micrel, inc. ksz9021rl/rn october 2009 9 m9999-101309-1.1 pin description ? ksz9021rl pin number pin name type (1) pin function 1 txrxp_a i/o media dependent interface[0], positive si gnal of differential pair 1000base-t mode: txrxp_a corresponds to bi_da+ fo r mdi configuration and bi_db+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_a is the positive transmit si gnal (tx+) for mdi configuration and the positive receive signal (rx+) fo r mdi-x configuration, respectively. 2 txrxm_a i/o media dependent interface[ 0], negative signal of differential pair 1000base-t mode: txrxm_a corresponds to bi_da- fo r mdi configuration and bi_db- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_a is the negative transmit si gnal (tx-) for mdi configuration and the negative receive signal (rx-) fo r mdi-x configuration, respectively. 3 agndh gnd analog ground 4 avddl p 1.2v analog v dd 5 avddl p 1.2v analog v dd 6 avddh p 3.3v analog v dd 7 txrxp_b i/o media dependent interface[1], positive si gnal of differential pair 1000base-t mode: txrxp_b corresponds to bi_db+ fo r mdi configuration and bi_da+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_b is the positive receive sign al (rx+) for mdi configuration and the positive transmit signal (tx+) fo r mdi-x configuration, respectively. 8 txrxm_b i/o media dependent interface[ 1], negative signal of differential pair 1000base-t mode: txrxm_b corresponds to bi_db- fo r mdi configuration and bi_da- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_b is the negative receive signal (rx-) for mdi configuration and the negative transmit signal (tx-) fo r mdi-x configuration, respectively. 9 agndh gnd analog ground 10 txrxp_c i/o media dependent interface[2], positive si gnal of differential pair 1000base-t mode: txrxp_c corresponds to bi_dc+ fo r mdi configuration and bi_dd+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_c is not used. 11 txrxm_c i/o media dependent interface[2], negative sign al of differential pair 1000base-t mode: txrxm_c corresponds to bi_dc- fo r mdi configuration and bi_dd- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_c is not used.
micrel, inc. ksz9021rl/rn october 2009 10 m9999-101309-1.1 pin number pin name type (1) pin function 12 avddl p 1.2v analog v dd 13 avddl p 1.2v analog v dd 14 txrxp_d i/o media dependent interface[3], positive si gnal of differential pair 1000base-t mode: txrxp_d corresponds to bi_dd+ fo r mdi configuration and bi_dc+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_d is not used. 15 txrxm_d i/o media dependent interface[3], negative sign al of differential pair 1000base-t mode: txrxm_d corresponds to bi_dd- fo r mdi configuration and bi_dc- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_d is not used. 16 avddh p 3.3v analog v dd 17 vss gnd digital ground 18 vss gnd digital ground 19 led2 / phyad1 i/o led output: programmable led2 output / config mode: the pull-up/pull-down value is latched as phyad[1] during power-up / reset. see ?strapping options? section for details. the led2 pin is programmed by the led_mode strapping option (pin 55), and is defined as follows. single led mode link pin state led definition link off h off link on (any speed) l on tri-color dual led mode pin state led definition link / activity led2 led1 led2 led1 link off h h off off 1000 link / no activity l h on off 1000 link / activity (rx, tx) toggle h blinking off 100 link / no activity h l off on 100 link / activity (rx, tx) h toggle off blinking 10 link / no activity l l on on 10 link / activity (rx, tx) toggle toggle blinking blinking for tri-color dual led mode, led2 works in conjunction with led1 (pin 21) to indicate 10 mbps link and activity. 20 dvddh p 3.3v / 2.5v digital v dd
micrel, inc. ksz9021rl/rn october 2009 11 m9999-101309-1.1 pin number pin name type (1) pin function 21 led1 / phyad0 i/o led output: programmable led1 output / config mode: the pull-up/pull-down value is latched as phyad[0] during power-up / reset. see ?strapping options? section for details. the led1 pin is programmed by the led_mode strapping option (pin 55), and is defined as follows. single led mode activity pin state led definition no activity h off activity (rx, tx) toggle blinking tri-color dual led mode pin state led definition link / activity led2 led1 led2 led1 link off h h off off 1000 link / no activity l h on off 1000 link / activity (rx, tx) toggle h blinking off 100 link / no activity h l off on 100 link / activity (rx, tx) h toggle off blinking 10 link / no activity l l on on 10 link / activity (rx, tx) toggle toggle blinking blinking for tri-color dual led mode, led1 works in conjunction with led2 (pin 19) to indicate 10 mbps link and activity. 22 dvddl p 1.2v digital v dd 23 vss gnd digital ground 24 txd0 i rgmii mode: rgmii td0 (transmit data 0) input 25 txd1 i rgmii mode: rgmii td1 (transmit data 1) input 26 txd2 i rgmii mode: rgmii td2 (transmit data 2) input 27 txd3 i rgmii mode: rgmii td3 (transmit data 3) input 28 vss gnd digital ground 29 dvddl p 1.2v digital v dd 30 dvddh p 3.3v / 2.5v digital v dd 31 tx_er i rgmii mode: this pin is not used and should be left as a no connect. 32 gtx_clk i rgmii mode: rgmii txc (transmit reference clock) input 33 tx_en i rgmii mode: rgmii tx_ctl (transmit control) input 34 vss gnd digital ground 35 dvddl p 1.2v digital v dd
micrel, inc. ksz9021rl/rn october 2009 12 m9999-101309-1.1 pin number pin name type (1) pin function 36 rxd3 / mode3 i/o rgmii mode: rgmii rd3 (receive data 3) output / config mode: the pull-up/pull-down value is latched as mode3 during power-up / reset. see ?strapping options? section for details. 37 dvddh p 3.3v / 2.5v digital v dd 38 rxd2 / mode2 i/o rgmii mode: rgmii rd2 (receive data 2) output / config mode: the pull-up/pull-down value is latched as mode2 during power-up / reset. see ?strapping options? section for details. 39 vss gnd digital ground 40 dvddl p 1.2v digital v dd 41 rxd1 / mode1 i/o rgmii mode: rgmii rd1 (receive data 1) output / config mode: the pull-up/pull-down value is latched as mode1 during power-up / reset. see ?strapping options? section for details. 42 rxd0 / mode0 i/o rgmii mode: rgmii rd0 (receive data 0) output / config mode: the pull-up/pull-down value is latched as mode0 during power-up / reset. see ?strapping options? section for details. 43 rx_dv / clk125_en i/o rgmii mode: rgmii rx_ctl (receive control) output / config mode: latched as clk125_ndo output enable during power-up / reset. see ?strapping options? section for details. 44 dvddh p 3.3v / 2.5v digital v dd 45 rx_er o rgmii mode: this pin is not used and should be left as a no connect. 46 rx_clk / phyad2 i/o rgmii mode: rgmii rxc (receive reference clock) output / config mode: the pull-up/pull-down value is latched as phyad[2] during power-up / reset. see ?strapping options? section for details. 47 crs o rgmii mode: this pin is not used and should be left as a no connect. 48 mdc ipu management data clock input this pin is the input reference clock for mdio (pin 49). 49 mdio ipu/o management data input / output this pin is synchronous to mdc (pin 48) and requires an external pull-up resistor to 3.3v digital v dd in a range from 1.0k ? to 4.7k ? . 50 col o rgmii mode: this pin is not used and should be left as a no connect. 51 int_n o interrupt output this pin provides a programmable interrupt output and requires an external pull-up resistor to 3.3v digital v dd in a range from 1.0k ? to 4.7k ? when active low. register 1bh is the interrupt control/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 14 sets the interrupt output to active low (default) or active high. 52 dvddl p 1.2v digital v dd 53 vss gnd digital ground 54 dvddl p 1.2v digital v dd 55 clk125_ndo / led_mode i/o 125mhz clock output this pin provides a 125mhz reference cl ock output option for use by the mac. / config mode: the pull-up/pull-down value is latched as led_mode during power-up / reset. see ?strapping options? section for details.
micrel, inc. ksz9021rl/rn october 2009 13 m9999-101309-1.1 pin number pin name type (1) pin function 56 reset_n ipu chip reset (active low) hardware pin configurations are strapped- in at the de-assertion (rising edge) of reset_n. see ?strapping options? section for more details. 57 ldo_o o on-chip 1.2v ldo controller output this pin drives the input gate of a p- channel mosfet to generate 1.2v for the chip?s core voltages. if 1.2v is provided by the system and this pin is not used, it can be left floating. 58 avddl_pll p 1.2v analog v dd for pll 59 xo o 25mhz crystal feedback this pin is a no connect if oscillator or external clock source is used. 60 xi i crystal / oscillator / external clock input 25mhz +/-50ppm tolerance 61 avddh p 3.3v analog v dd 62 iset i/o set transmit output level connect a 4.99k ? 1% resistor to ground on this pin. 63 agndh_bg gnd analog ground 64 avddh p 3.3v analog v dd e-pad e-pad gnd exposed pad on bottom of chip connect e-pad to ground. note: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipu = input with internal pull-up. ipu/o = input with internal pull-up / output.
micrel, inc. ksz9021rl/rn october 2009 14 m9999-101309-1.1 strapping options ? ksz9021rl pin number pin name type (1) pin function 46 19 21 phyad2 phyad1 phyad0 i/o i/o i/o the phy address, phyad[2:0], is latched at power-up / reset and is configurable to any value from 1 to 7. each phy address bit is configured as follows: pull-up = 1 pull-down = 0 phy address bits [4:3] ar e always set to ?00?. 36 38 41 42 mode3 mode2 mode1 mode0 i/o i/o i/o i/o the mode[3:0] strap-in pins are latch ed at power-up / reset and are defined as follows: mode[3:0] mode 0000 reserved ? not used 0001 reserved ? not used 0010 reserved ? not used 0011 reserved ? not used 0100 nand tree mode 0101 reserved ? not used 0110 reserved ? not used 0111 chip power down mode 1000 reserved ? not used 1001 reserved ? not used 1010 reserved ? not used 1011 reserved ? not used 1100 rgmii mode ? advertise 1000base-t full-duplex only 1101 rgmii mode ? advertise 1000base-t full and half-duplex only 1110 rgmii mode ? advertise all ca pabilities (10/100/1000 speed half/full duplex),except 1000base-t half-duplex 1111 rgmii mode ? advertise all capabilities (10/100/1000 speed half/full duplex) 43 clk125_en i/o clk125_en is latched at powe r-up / reset and is defined as follows: pull-up = enable 125mhz clock output pull-down = disable 125mhz clock output pin 55 (clk125_ndo) provides the 125mhz re ference clock output option for use by the mac. 55 led_mode i/o led_mode is latched at po wer-up / reset and is defined as follows: pull-up = single led mode pull-down = tri-color dual led mode note: 1. i/o = bi-directional. pin strap-ins are latched during power-up or reset. in some systems, the mac receive input pins may be driven during power-up or reset, and consequently cause the phy strap-in pins on the rgmii signals to be latched to the incorrect configuration. in this case, it is recommended to add exte rnal pull-ups/pull-downs on the phy strap-in pins to ensure the phy is configured to the correct pin strap-in mode.
micrel, inc. ksz9021rl/rn october 2009 15 m9999-101309-1.1 pin configuration ? ksz9021rn 48-pin qfn (top view)
micrel, inc. ksz9021rl/rn october 2009 16 m9999-101309-1.1 pin description ? ksz9021rn pin number pin name type (1) pin function 1 avddh p 3.3v analog v dd 2 txrxp_a i/o media dependent interface[0], positive si gnal of differential pair 1000base-t mode: txrxp_a corresponds to bi_da+ fo r mdi configuration and bi_db+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_a is the positive transmit si gnal (tx+) for mdi configuration and the positive receive signal (rx+) fo r mdi-x configuration, respectively. 3 txrxm_a i/o media dependent interface[ 0], negative signal of differential pair 1000base-t mode: txrxm_a corresponds to bi_da- fo r mdi configuration and bi_db- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_a is the negative transmit si gnal (tx-) for mdi configuration and the negative receive signal (rx-) fo r mdi-x configuration, respectively. 4 avddl p 1.2v analog v dd 5 txrxp_b i/o media dependent interface[1], positive si gnal of differential pair 1000base-t mode: txrxp_b corresponds to bi_db+ fo r mdi configuration and bi_da+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_b is the positive receive sign al (rx+) for mdi configuration and the positive transmit signal (tx+) fo r mdi-x configuration, respectively. 6 txrxm_b i/o media dependent interface[ 1], negative signal of differential pair 1000base-t mode: txrxm_b corresponds to bi_db- fo r mdi configuration and bi_da- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_b is the negative receive signal (rx-) for mdi configuration and the negative transmit signal (tx-) fo r mdi-x configuration, respectively. 7 txrxp_c i/o media dependent interface[2], positive si gnal of differential pair 1000base-t mode: txrxp_c corresponds to bi_dc+ fo r mdi configuration and bi_dd+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_c is not used. 8 txrxm_c i/o media dependent interface[ 2], negative signal of differential pair 1000base-t mode: txrxm_c corresponds to bi_dc- fo r mdi configuration and bi_dd- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_c is not used. 9 avddl p 1.2v analog v dd
micrel, inc. ksz9021rl/rn october 2009 17 m9999-101309-1.1 pin number pin name type (1) pin function 10 txrxp_d i/o media dependent interface[3], positive si gnal of differential pair 1000base-t mode: txrxp_d corresponds to bi_dd+ fo r mdi configuration and bi_dc+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_d is not used. 11 txrxm_d i/o media dependent interface[3], negative sign al of differential pair 1000base-t mode: txrxm_d corresponds to bi_dd- fo r mdi configuration and bi_dc- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_d is not used. 12 avddh p 3.3v analog v dd 13 vss_ps gnd digital ground 14 dvddl p 1.2v digital v dd 15 led2 / phyad1 i/o led output: programmable led2 output / config mode: the pull-up/pull-down value is latched as phyad[1] during power-up / reset. see ?strapping options? section for details. the led2 pin is programmed by the led_mode strapping option (pin 41), and is defined as follows. single led mode link pin state led definition link off h off link on (any speed) l on tri-color dual led mode pin state led definition link / activity led2 led1 led2 led1 link off h h off off 1000 link / no activity l h on off 1000 link / activity (rx, tx) toggle h blinking off 100 link / no activity h l off on 100 link / activity (rx, tx) h toggle off blinking 10 link / no activity l l on on 10 link / activity (rx, tx) toggle toggle blinking blinking for tri-color dual led mode, led2 works in conjunction with led1 (pin 17) to indicate 10 mbps link and activity. 16 dvddh p 3.3v / 2.5v digital v dd
micrel, inc. ksz9021rl/rn october 2009 18 m9999-101309-1.1 pin number pin name type (1) pin function 17 led1 / phyad0 i/o led output: programmable led1 output / config mode: the pull-up/pull-down value is latched as phyad[0] during power-up / reset. see ?strapping options? section for details. the led1 pin is programmed by the led_mode strapping option (pin 41), and is defined as follows. single led mode activity pin state led definition no activity h off activity (rx, tx) toggle blinking tri-color dual led mode pin state led definition link / activity led2 led1 led2 led1 link off h h off off 1000 link / no activity l h on off 1000 link / activity (rx, tx) toggle h blinking off 100 link / no activity h l off on 100 link / activity (rx, tx) h toggle off blinking 10 link / no activity l l on on 10 link / activity (rx, tx) toggle toggle blinking blinking for tri-color dual led mode, led1 works in conjunction with led2 (pin 15) to indicate 10 mbps link and activity. 18 dvddl p 1.2v digital v dd 19 txd0 i rgmii mode: rgmii td0 (transmit data 0) input 20 txd1 i rgmii mode: rgmii td1 (transmit data 1) input 21 txd2 i rgmii mode: rgmii td2 (transmit data 2) input 22 txd3 i rgmii mode: rgmii td3 (transmit data 3) input 23 dvddl p 1.2v digital v dd 24 gtx_clk i rgmii mode: rgmii txc (transmit reference clock) input 25 tx_en i rgmii mode: rgmii tx_ctl (transmit control) input 26 dvddl p 1.2v digital v dd 27 rxd3 / mode3 i/o rgmii mode: rgmii rd3 (receive data 3) output / config mode: the pull-up/pull-down value is latched as mode3 during power-up / reset. see ?strapping options? section for details. 28 rxd2 / mode2 i/o rgmii mode: rgmii rd2 (receive data 2) output / config mode: the pull-up/pull-down value is latched as mode2 during power-up / reset. see ?strapping options? section for details. 29 vss gnd digital ground 30 dvddl p 1.2v digital v dd 31 rxd1 / mode1 i/o rgmii mode: rgmii rd1 (receive data 1) output / config mode: the pull-up/pull-down value is latched as mode1 during power-up / reset. see ?strapping options? section for details.
micrel, inc. ksz9021rl/rn october 2009 19 m9999-101309-1.1 pin number pin name type (1) pin function 32 rxd0 / mode0 i/o rgmii mode: rgmii rd0 (receive data 0) output / config mode: the pull-up/pull-down value is latched as mode0 during power-up / reset. see ?strapping options? section for details. 33 rx_dv / clk125_en i/o rgmii mode: rgmii rx_ctl (receive control) output / config mode: latched as clk125_ndo output enable during power-up / reset. see ?strapping options? section for details. 34 dvddh p 3.3v / 2.5v digital v dd 35 rx_clk / phyad2 i/o rgmii mode: rgmii rxc (receive reference clock) output / config mode: the pull-up/pull-down value is latched as phyad[2] during power-up / reset. see ?strapping options? section for details. 36 mdc ipu management data clock input this pin is the input reference clock for mdio (pin 37). 37 mdio ipu/o management data input / output this pin is synchronous to mdc (pin 36) and requires an external pull-up resistor to 3.3v digital v dd in a range from 1.0k ? to 4.7k ? . 38 int_n o interrupt output this pin provides a programmable interrupt output and requires an external pull-up resistor to 3.3v digital v dd in a range from 1.0k ? to 4.7k ? when active low. register 1bh is the interrupt control/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 14 sets the interrupt output to active low (default) or active high. 39 dvddl p 1.2v digital v dd 40 dvddh p 3.3v / 2.5v digital v dd 41 clk125_ndo / led_mode i/o 125mhz clock output this pin provides a 125mhz reference cl ock output option for use by the mac. / config mode: the pull-up/pull-down value is latched as led_mode during power-up / reset. see ?strapping options? section for details. 42 reset_n ipu chip reset (active low) hardware pin configurations are strapped- in at the de-assertion (rising edge) of reset_n. see ?strapping options? section for more details. 43 ldo_o o on-chip 1.2v ldo controller output this pin drives the input gate of a p- channel mosfet to generate 1.2v for the chip?s core voltages. if 1.2v is provided by the system and this pin is not used, it can be left floating. 44 avddl_pll p 1.2v analog v dd for pll 45 xo o 25mhz crystal feedback this pin is a no connect if oscillator or external clock source is used. 46 xi i crystal / oscillator / external clock input 25mhz +/-50ppm tolerance 47 avddh p 3.3v analog v dd 48 iset i/o set transmit output level connect a 4.99k ? 1% resistor to ground on this pin. paddle p_gnd gnd exposed paddle on bottom of chip connect p_gnd to ground.
micrel, inc. ksz9021rl/rn october 2009 20 m9999-101309-1.1 note: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipu = input with internal pull-up. ipu/o = input with internal pull-up / output.
micrel, inc. ksz9021rl/rn october 2009 21 m9999-101309-1.1 strapping options ? ksz9021rn pin number pin name type (1) pin function 35 15 17 phyad2 phyad1 phyad0 i/o i/o i/o the phy address, phyad[2:0], is latched at power-up / reset and is configurable to any value from 1 to 7. each phy address bit is configured as follows: pull-up = 1 pull-down = 0 phy address bits [4:3] ar e always set to ?00?. 27 28 31 32 mode3 mode2 mode1 mode0 i/o i/o i/o i/o the mode[3:0] strap-in pins are latch ed at power-up / reset and are defined as follows: mode[3:0] mode 0000 reserved ? not used 0001 reserved ? not used 0010 reserved ? not used 0011 reserved ? not used 0100 nand tree mode 0101 reserved ? not used 0110 reserved ? not used 0111 chip power down mode 1000 reserved ? not used 1001 reserved ? not used 1010 reserved ? not used 1011 reserved ? not used 1100 rgmii mode ? advertise 1000base-t full-duplex only 1101 rgmii mode ? advertise 1000base-t full and half-duplex only 1110 rgmii mode ? advertise all ca pabilities (10/100/1000 speed half/full duplex),except 1000base-t half-duplex 1111 rgmii mode ? advertise all capabilities (10/100/1000 speed half/full duplex) 33 clk125_en i/o clk125_en is latched at powe r-up / reset and is defined as follows: pull-up = enable 125mhz clock output pull-down = disable 125mhz clock output pin 41 (clk125_ndo) provides the 125mhz re ference clock output option for use by the mac. 41 led_mode i/o led_mode is latched at po wer-up / reset and is defined as follows: pull-up = single led mode pull-down = tri-color dual led mode note: 1. i/o = bi-directional. pin strap-ins are latched during power-up or reset. in some systems, the mac receive input pins may be driven during power-up or reset, and consequently cause the phy strap-in pins on the rgmii signals to be latched to the incorrect configuration. in this case, it is recommended to add exte rnal pull-ups/pull-downs on the phy strap-in pins to ensure the phy is configured to the correct pin strap-in mode.
micrel, inc. ksz9021rl/rn october 2009 22 m9999-101309-1.1 functional overview the ksz9021rl/rn is a completely integrated triple spe ed (10base-t/100base-tx/1000base- t) ethernet physical layer transceiver solution for transmission and reception of data ov er a standard cat-5 unshielded twisted pair (utp) cable. its on-chip proprietary 1000base-t transceiver and m anchester/mlt-3 signaling-based 10base-t/100base-tx transceivers are all ieee 802.3 compliant. the ksz9021rl/rn reduces board cost and simplifies board lay out by using on-chip terminat ion resistors for the four differential pairs and by integrating a ldo controller to drive a low cost mosfet to supply the 1.2v core. on the copper media interface, the ksz9021rl/rn can au tomatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified in the ieee 802. 3 standard for 1000base-t operation. the ksz9021rl/rn provides the rgmii interface for a direct and seamless connection to rgmii macs in gigabit ethernet processors and switches for da ta transfer at 10/100/1000mbps speed. the following figure shows a high-level block diagram of the ksz9021rl/rn. figure 1. ksz9021rl/rn block diagram
micrel, inc. ksz9021rl/rn october 2009 23 m9999-101309-1.1 functional description: 10 base-t/100base-tx transceiver 100base-tx transmit the 100base-tx transmit function performs parallel to se rial conversion, 4b/5b codi ng, scrambling, nrz-to-nrzi conversion, and mlt-3 encoding and transmission. the circuitry starts with a parallel-to-s erial conversion, which converts the rgm ii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transm itted in mlt-3 current output. the output current is set by an external 4.99k ? 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and co mplies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function perfor ms adaptive equalization, dc restoration, mlt-3-to-n rzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cabl e characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against envir onmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt-3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 1 25mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this si gnal is sent through the de-sc rambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the rgmii format and provided as the input data to the mac. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectr um of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047- bit non-repetitive sequence, and the rece iver then de-scrambles the incoming data stream using the same sequence as at the transmitter. 10base-t transmit the output 10base-t driver is incorporated into the 100base-tx driver to allow transmission with the same magnetic. they are internally wave-shaped and pre-emphasized into typical outputs of 2.5v amplitude. the harmonic contents are at least 31 db below the fundamental when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a phase-locked loop (pll) perform the decoding function. t he manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 300 mv or with short pulse widths in order to prevent noises at the receive inputs from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz9021rl/rn decodes a data frame. the receiver clock is maintained active during idle periods in between receiving data frames.
micrel, inc. ksz9021rl/rn october 2009 24 m9999-101309-1.1 functional description: 1000base-t transceiver the 1000base-t transceiver is based on a mixed-signal/digital signal processing (dsp) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-ta lk cancellers, precision clock recovery scheme, and power efficient line drivers. the following figure shows a high-level block diagram of a si ngle channel of the 1000base-t transceiver for one of the four differential pairs. clk generation baseline wander compensation echo canceller transmit block next canceller next canceller next canceller rx- adc agc + ffe slicer clock & phase recovery auto-negotiation pma state machines mii registers mii management control dfe analog hybrid pcs state machines pair swap & align unit descrambler + decoder side-stream scrambler & symbol encoder led driver xtal other channels tx signal rx signal figure 2. ksz9021rl/rn 1000base-t block diagram ? single channel analog echo cancellation circuit in 1000base-t mode, the analog echo cancellation circuit helps to reduce the near-end echo. this analog hybrid circuit relieves the burden of the adc and the adaptive equalizer. this circuit is disabled in 10base-t/100base-tx mode. automatic gain control (agc) in 1000base-t mode, the automatic gain contro l (agc) circuit provides initial gain adjustment to boost up the signal level. this pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal. analog-to-digital converter (adc) in 1000base-t mode, the analog-to-digital c onverter (adc) digitizes the incoming si gnal. adc performance is essential to the overall performance of the transceiver. this circuit is disabled in 10base-t/100base-tx mode.
micrel, inc. ksz9021rl/rn october 2009 25 m9999-101309-1.1 timing recovery circuit in 1000base-t mode, the mixed-signal clock recovery circuit, together with the digital phase locked loop, is used to recover and track the incoming timing information from the re ceived data. the digital phase locked loop has very low long- term jitter to maximize the signal-to-noise ratio of the receive signal. the 1000base-t slave phy is required to transmit the exact receive clock frequency recovered from the received data back to the 1000base-t master phy. otherwise, the master and slave will not be synchronized after long transmission. additionally, this helps to facilitate echo cancellation and next removal. adaptive equalizer in 1000base-t mode, the adaptive equalizer provides the following functions: ? detection for partial response signaling ? removal of next and echo noise ? channel equalization signal quality is degraded by residual echo that is not removed by the analog hybrid and echo due to impedance mismatch. the ksz9021rl/rn employs a digital echo canceller to further reduce echo components on the receive signal. in 1000base-t mode, the data transmission and reception occurs simultaneously on all four pairs of wires (four channels). this results in high frequency cross-talk coming fr om adjacent wires. the ksz9021rl/rn employs three next cancellers on each receive channel to minimize t he cross-talk induced by the other three channels. in 10base-t/100base-tx mode, the adaptiv e equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. trellis encoder and decoder in 1000base-t mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4d-pam5 symbols. the initial scrambler seed is determined by the specific phy address to reduce emi when more than one ksz9021rl/rn is used on the same board. on the receiving si de, the idle stream is examined first. the scrambler seed, pair skew, pair order and polarity have to be resolved thro ugh the logic. the incoming 4d-pam5 data is then converted into 9-bit symbols and then de-scrambled into 8-bit data. functional description: 10/10 0/1000 transceiver features auto mdi/mdi-x the automatic mdi/mdi-x feature eliminates the need to deter mine whether to use a straight cable or a crossover cable between the ksz9021rl/rn and its link partner. this auto-sense function detects the mdi/mdi-x pair mapping from the link partner, and then assigns the mdi/mdi-x pair mapping of the ksz9021rl/rn accordingly. the following table shows the ksz9021rl/rn 10/100/1000 pin-out assignments for mdi/mdi-x pin mapping. mdi mdi-x pin (rj-45 pair) 1000base-t 100base-tx 10base-t 1000base-t 100base-tx 10base-t txrxp/m_a (1,2) a+/- tx+/- tx+/- b+/- rx+/- rx+/- txrxp/m_b (3,6) b+/- rx+/- rx+/- a+/- tx+/- tx+/- txrxp/m_c (4,5) c+/- not used not used d+/- not used not used txrxp/m_d (7,8) d+/- not used not used c+/- not used not used table 1. mdi / mdi-x pin mapping auto mdi/mdi-x is enabled by default. it is disabled by writ ing a one to register 28 (1ch) bit 6. mdi and mdi-x mode is set by register 28 (1ch) bit 7 if auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and re ceive data paths is recommended to support auto mdi/mdi-x.
micrel, inc. ksz9021rl/rn october 2009 26 m9999-101309-1.1 pair- swap, alignment, and polarity check in 1000base-t mode, the ksz9021rl/rn ? detects incorrect channel order and automatically restore the pair order for the a, b, c, d pairs (four channels) ? supports 5010n s difference in propagation delay between pairs of channels in accordan ce with the ieee 802.3 standard, and automatically corrects the data skew so the corrected 4-pairs of dat a symbols are synchronized incorrect pair polarities of the differential signal s are automatically corrected for all speeds. wave shaping, slew rate control and partial response in communication systems, signal transmission encoding meth ods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. ? for 1000base-t, a special partial response signaling method is used to provide the band-limiting feature for the transmission path. ? for 100base-tx, a simple slew rate control method is used to minimize emi. ? for 10base-t, pre-emphasis is used to ex tend the signal quality through the cable. pll clock synthesizer the ksz9021rl/rn generates 125mhz, 25mhz and 10mhz clocks fo r system timing. internal clocks are generated from the external 25mhz crystal or reference clock. auto-negotiation the ksz9021rl/rn conforms to the auto-ne gotiation protocol, defined in clause 28 of the ieee 802.3 specification. auto-negotiation allows utp (unshielded twisted pair) link par tners to select the highest common mode of operation. during auto-negotiation, link partners adv ertise capabilities across the utp link to each other, and then compare their own capabilities with those they received from their link partne rs. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? priority 1: 1000base-t, full-duplex ? priority 2: 1000base-t, half-duplex ? priority 3: 100base-tx, full-duplex ? priority 4: 100base-tx, half-duplex ? priority 5: 10base-t, full-duplex ? priority 6: 10base-t, half-duplex if auto-negotiation is not supported or the ksz9021rl/rn link pa rtner is forced to bypass auto-negotiation for 10base-t and 100base-tx modes, then the ksz9021rl/rn sets its operati ng mode by observing the input signal at its receiver. this is known as parallel detection, and allows the ksz9021r l/rn to establish a link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. the auto-negotiation link up process is shown in the following flow chart.
micrel, inc. ksz9021rl/rn october 2009 27 m9999-101309-1.1 start auto negotiation force link setting listen for 10baset link pulses listen for 100basetx idles attempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow no yes yes no figure 3. auto-negotiation flow chart for 1000base-t mode, auto-negotiation is required and always used to establish link. during 1000base-t auto- negotiation, master and slave configuration is first resolved between link partners, and then link is established with the highest common capabilities between link partners. auto-negotiation is enabled by default at power-up or afte r hardware reset. afterwards, auto-negotiation can be enabled or disabled through register 0 bit 12. if auto-negotiation is di sabled, then the speed is set by register 0 bits 6 and 13, and the duplex is set by register 0 bit 8. if the speed is changed on the fly, then the link goes down and ei ther auto-negotiation or parallel detection will initiate unt il a common speed between ksz9021rl/rn and its link partner is re-established for link. if link is already established, and there is no change of speed on the fly, then the changes w ill not take effect unless either auto-negotiation is restarted through register 0 bit 9, or a li nk down to link up transition occurs (i.e., disconnecting and reconnecting the cable). after auto-negotiation is completed, the lin k status is updated in register 1 and t he link partner capabilities are updated in registers 5, 6, and 10. the auto-negotiation finite state machines employ interval ti mers to manage the auto-negotiation process. the duration of these timers under normal operating condition s are summarized in the following table.
micrel, inc. ksz9021rl/rn october 2009 28 m9999-101309-1.1 auto-negotiation interval timers time duration transmit burst interval 16 ms transmit pulse interval 68 us flp detect minimum time 17.2 us flp detect maximum time 185 us receive minimum burst interval 6.8 ms receive maximum burst interval 112 ms data detect minimum interval 35.4 us data detect maximum interval 95 us nlp test minimum interval 4.5 ms nlp test maximum interval 30 ms link loss time 52 ms break link time 1480 ms parallel detection wait time 830 ms link enable wait time 1000 ms table 2. auto-negotiation timers rgmii interface the reduced gigabit media independent interface (rgmii) is co mpliant with the rgmii version 1.3 specification. it provides a common interface between rgmii phys and macs, and has the following key characteristics: ? pin count is reduced from 24 pins for the ieee gigabit media independent interface (gmii) to 12 pins for rgmii. ? all speeds (10mbps, 100mbps, and 1000mbps) are supported at both half and full duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4-bit wide, a nibble. in rgmii operation, the rgmii pins function as follow: ? the mac sources the transmit reference clock, txc, at 125mhz for 1000mbps, 25mhz for 100mbps and 2.5mhz for 10mbps. ? the phy recovers and sources the receive reference clock, rxc, at 125mhz for 1000mbps, 25mhz for 100mbps and 2.5mhz for 10mbps. ? for 1000base-t, the transmit data, txd[3:0], is pr esented on both edges of txc, and the received data, rxd[3:0], is clocked out on both edges of the recovered 125 mhz clock, rxc. ? for 10base-t/100base-tx, the mac will hold tx_ctl low until both phy and mac operate at the same speed. during the speed transition, the receive clock will be stretched on either positive or negative pulse to ensure that no clock glitch is presented to the mac at any time. ? tx_er and rx_er are combined with tx_en and rx_dv, respectively, to form tx_ctl and rx_ctl. these two rgmii control signals are valid at the falling clock edge. after power-up or reset, the ksz9021rl/rn is configured to rgmii mode if the mode[3:0] strap-in pins are set to one of the rgmii mode capability options. see strappi ng options section for available options. the ksz9021rl/rn has the option to output a low jitter 125m hz reference clock on the clk125_ndo pin. this clock provides a lower cost reference clock alternative for rgmii ma cs that require a 125mhz crystal or oscillator. the 125mhz clock output is enabled after power-up or reset if the clk125_en strap-in pin is pulled high.
micrel, inc. ksz9021rl/rn october 2009 29 m9999-101309-1.1 rgmii signal definition the following table describes the rgmii signals. refer to the rgmii version 1.3 specification for more detailed information. rgmii signal name (per spec) rgmii signal name (per ksz9021rl/rn) pin type (with respect to phy) pin type (with respect to mac) description txc gtx_clk input output transmit reference clock (125mhz for 1000mbps, 25mhz for 100mbps, 2.5mhz for 10mbps) tx_ctl tx_en input output transmit control txd[3:0] txd[3:0] input ou tput transmit data [3:0] rxc rx_clk output input receive reference clock (125mhz for 1000mbps, 25mhz for 100mbps, 2.5mhz for 10mbps) rx_ctl rx_dv output input receive control rxd[3:0] rxd[3:0] output input receive data [3:0] table 3. rgmii signal definition rgmii signal diagram the ksz9021rl/rn rgmii pin connections to the mac are shown in the following figure. ksz9021rl/rn txc tx_ctl txd[3:0] rxc rx_ctl rxd[3:0] gtx_clk tx_en txd[3:0] rx_clk rx_dv rxd[3:0] rgmii ethernet mac figure 4. ksz9021rl/rn rgmii interface
micrel, inc. ksz9021rl/rn october 2009 30 m9999-101309-1.1 rgmii in-band status the ksz9021rl/rn can provide in-band status to the mac during the inter-frame gap when rx_dv is de-asserted. rgmii in-band status is disabled by default. it is enabl ed by writing a one to extended register 256 (100h) bit 8. the in-band status is sent to the mac using the rxd[3:0] dat a pins, and is described in the following table. rx_dv rxd3 rxd[2:1] rxd0 0 (valid only when rx_dv is low and register 256 bit 8 is set to 1) duplex status 0 = half-duplex 1 = full-duplex rx_clk clock speed 00 =2.5mhz 01 =25mhz 10 =125mhz 11 = reserved link status 0 = link down 1 = link up table 4. rgmii in-band status mii management (miim) interface the ksz9021rl/rn supports the ieee 802.3 mii management inte rface, also known as the management data input / output (mdio) interface. this interfac e allows upper-layer devices to monitor and control the state of the ksz9021rl/rn. an external device with miim capability is used to read the phy status and/or configure the phy setti ngs. further detail on the miim interface can be found in clause 22.2.4.5 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates t he clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the aforementi oned physical connection that allows an external controller to communicate with one or more ksz9021rl/rn device. each ksz9021rl/rn device is assigned a phy address between 1 and 7 by the phyad[2:0] strapping pins. ? a 32 register address space to access the ksz9021rl/rn ieee defined registers, v endor specific registers and extended registers. see register map section. the following table shows the mii manag ement frame format for the ksz9021rl/rn. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z table 5. mii management frame format ? for ksz9021rl/rn interrupt (int_n) the int_n pin is an optional interrupt signal that is used to inform the external controlle r that there has been a status update in the ksz9021rl/rn phy register. bits [15:8] of register 27 (1bh) are th e interrupt control bits to enable and disable the conditions for asserting the int_n signal. bits [7:0] of register 27 (1bh) are the interrupt status bits to indicat e which interrupt conditions have occurred. the interrupt stat us bits are cleared after reading register 27 (1bh). bit 14 of register 31 (1fh) sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor co mplete access to the ksz9021rl/rn control and status registers. additionally, an interrupt pi n eliminates the need for the processor to poll the phy for status change.
micrel, inc. ksz9021rl/rn october 2009 31 m9999-101309-1.1 led mode the ksz9021rl/rn provides two programmable led output pi ns, led2 and led1, which are configurable to support two led modes. the led mode is configur ed by the led_mode strap-in pin. it is latched at power-up/reset and is defined as follows: ? pull-up: single led mode ? pull-down: tri-color dual led mode single led mode in single led mode, the led2 pin indicate s the link status while the led1 pin indi cates the activity status, as shown in the following table. led pin pin state led definition link / activity h off link off led2 l on link on (any speed) h off no activity led1 toggle blinking activity (rx, tx) table 6. single led mode ? pin definition tri-color dual led mode in tri-color dual led mode, the link and activity status are indicated by the le d2 pin for 1000base-t, by the led1 pin for 100base-tx, and by both led2 and led1 pin, working in conjunction, for 10base-t. this is summarized in the following table. led pin (state) led pin (definition) led2 led1 led2 led1 link / activity h h off off link off l h on off 1000 link / no activity toggle h blinking off 1000 link / activity (rx, tx) h l off on 100 link / no activity h toggle off blinking 100 link / activity (rx, tx) l l on on 10 link / no activity toggle toggle blinking blinking 10 link / activity (rx, tx) table 7. tri-color dual led mode ? pin definition each led output pin can directly drive a led with a series resistor (typically 220 ? to 470 ? ). for activity indication, the led output toggles at approximat ely 12.5hz (80ms) to ensure visibility to the human eye.
micrel, inc. ksz9021rl/rn october 2009 32 m9999-101309-1.1 nand tree support the ksz9021rl/rn provides parametric nand tree support for fault detection between chip i/os and board. nand tree mode is enabled at power-up / reset with the mode[3:0] strap-in pins set to 0100. the following tables list the nand tree pin order for ksz9021rl and ksz9021rn. pin description led2 input led1 input txd0 input txd1 input txd2 input txd3 input tx_er input gtx_clk input tx_en input rx_dv input rx_er input rx_clk input crs input col input int_n input mdc input mdio input clk125_ndo output table 8. nand tree test pin order ? for ksz9021rl pin description led2 input led1 input txd0 input txd1 input txd2 input txd3 input gtx_clk input tx_en input rx_dv input rx_clk input int_n input mdc input mdio input clk125_ndo output table 9. nand tree test pin order ? for ksz9021rn
micrel, inc. ksz9021rl/rn october 2009 33 m9999-101309-1.1 power management the ksz9021rl/rn offers the following power management modes: power saving mode this mode is a ksz9021rl/rn green feature to reduce power c onsumption when the cable is unplugged. it is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). software power down mode this mode is used to power down the ksz9021rl/rn device when it is not in use after power-up. power down mode is enabled by writing a one to register 0h bit 11. in the power do wn state, the ksz9021rl/rn disables all internal functions, except for the mii management interface. the ksz9021rl/rn ex its power down mode after writing a zero to register 0h bit 11. chip power down mode this mode provides the lowest power state for the ksz9021rl/rn when it is not in use and is mounted on the board. chip power down mode is enabled at power-up / reset with the mode[3:0] strap-in pins set to 0111. the ksz9021rl/rn exits chip power down mode when a hardwa re reset is applied to the reset_n pin with the mode[3:0] strap-in pins set to an operating mode other than chip power down mode. register map the ieee 802.3 specification provides a 32 register address space for the phy. registers 0 thru 15 are standard phy registers, defined per the specif ication. registers 16 thru 31 ar e vendor specific registers. the ksz9021rl/rn uses the ieee provided register space for ieee defined regist ers and vendor spec ific registers, and uses the following registers to access extended registers: ? register 11 (bh) for extended register ? control ? register 12 (ch) for extended register ? data write ? register 13 (dh) for extended register ? data read examples: ? extended register read // read from o peration mode strap status register 1. write register 11 (bh) with 010 3h // set register 259 (103h) for read 2. read register 13 (dh) // read register value ? extended register write // write to o peration mode strap override register 1. write register 11 (bh) with 8102h // set register 258 (102h) for write 2. write register 12 (ch) with 0010h // write 0010h value to register to set nand tree mode register number (hex) description ieee defined registers 0 (0h) basic control 1 (1h) basic status 2 (2h) phy identifier 1 3 (3h) phy identifier 2 4 (4h) auto-negotiation advertisement 5 (5h) auto-negotiation link partner ability 6 (6h) auto-negotiation expansion 7 (7h) auto-negotiation next page
micrel, inc. ksz9021rl/rn october 2009 34 m9999-101309-1.1 register number (hex) description 8 (8h) auto-negotiation link partner next page ability 9 (9h) 1000base-t control 10 (ah) 1000base-t status 11 (bh) extended register ? control 12 (ch) extended register ? data write 13 (dh) extended register ? data read 14 (eh) reserved 15 (fh) extended ? mii status vendor specific registers 16 (10h) reserved 17 (11h) remote l oopback, led mode 18 (12h) linkmd ? ? cable diagnostic 19 (13h) digital pma/pcs status 20 (14h) reserved 21 (15h) rxer counter 22 (16h) ? 26 (1ah) reserved 27 (1bh) interrupt control/status 28 (1ch) digital debug control 1 29 (1dh) ? 30 (1eh) reserved 31 (1fh) phy control extended registers 256 (100h) common control 257 (101h) strap status 258 (102h) operation mode strap override 259 (103h) operation mo de strap status 260 (104h) rgmii clock and control pad skew 261 (105h) rgmii rx data pad skew 263 (107h) analog test register register description ieee defined registers address name description mode (1) default register 0 (0h) ? basic control 0.15 reset 1 = software phy reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loop-back 1 = loop-back mode 0 = normal operation rw 0
micrel, inc. ksz9021rl/rn october 2009 35 m9999-101309-1.1 address name description mode (1) default 0.13 speed select (lsb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000mbps [0,1] = 100mbps [0,0] = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw hardware setting 0.12 auto- negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiation result overrides settings in register 0.13, 0.8 and 0.6. rw 1 0.11 power down 1 = power down mode 0 = normal operation rw 0 0.10 isolate 1 = electrical is olation of phy from rgmii 0 = normal operation rw 0 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw hardware setting 0.7 reserved rw 0 0.6 speed select (msb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000mbps [0,1] = 100mbps [0,0] = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw 0 0.5:0 reserved ro 00_0000 register 1 (1h) ? basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full duplex 1 = capable of 100mbps full-duplex 0 = not capable of 100mbps full-duplex ro 1 1.13 100base-tx half duplex 1 = capable of 100mbps half-duplex 0 = not capable of 100mbps half-duplex ro 1 1.12 10base-t full duplex 1 = capable of 10mbps full-duplex 0 = not capable of 10mbps full-duplex ro 1 1.11 10base-t half duplex 1 = capable of 10mbps half-duplex 0 = not capable of 10mbps half-duplex ro 1 1.10:9 reserved ro 00 1.8 extended status 1 = extended status information in reg. 15. 0 = no extended status information in reg. 15. ro 1
micrel, inc. ksz9021rl/rn october 2009 36 m9999-101309-1.1 address name description mode (1) default 1.7 reserved ro 0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = capable to perform auto-negotiation 0 = not capable to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers ro 1 register 2 (2h) ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0022h register 3 (3h) ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24 th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manuf acturer?s model number ro 10_0001 3.3:0 revision number four bit manufacturer?s revision number ro indicates silicon revision register 4 (4h) ? auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved ro 0 4.11:10 pause [4 .11, 4.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric & asymmetric pause (local device) rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability rw 1
micrel, inc. ksz9021rl/rn october 2009 37 m9999-101309-1.1 address name description mode (1) default 4.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability rw 1 4.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability rw 1 4.4:0 selector field [ 00001] = ieee 802.3 rw 0_0001 register 5 (5h) ? auto-ne gotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved ro 0 5.11:10 pause [5 .11, 5.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric & asymmetric pause (local device) rw 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability ro 0 5.4:0 selector field [0000 1] = ieee 802.3 ro 0_0000 register 6 (6h) ? auto-negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection. ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0
micrel, inc. ksz9021rl/rn october 2009 38 m9999-101309-1.1 address name description mode (1) default 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7 (7h) ? auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow 0 = last page rw 0 7.14 reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8 (8h) ? auto-negotiati on link partner next page ability 8.15 next page 1 = additional next page(s) will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 9 (9h) ? 1000base-t control
micrel, inc. ksz9021rl/rn october 2009 39 m9999-101309-1.1 address name description mode (1) default 9:15:13 test mode bits trans mitter test mode operations [9.15:13] mode [000] normal operation [001] test mode 1 ?transmit waveform test [010] test mode 2 ?transmit jitter test in master mode [011] test mode 3 ?transmit jitter test in slave mode [100] test mode 4 ?transmitter distortion test [101] reserved, operations not identified [110] reserved, operations not identified [111] reserved, operations not identified rw 000 9.12 master- slave manual config enable 1 = enable master-slave manual configuration value 0 = disable master-slave manual configuration value rw 0 9.11 master- slave manual config value 1 = configure phy as master during master-slave negotiation 0 = configure phy as slave during master- slave negotiation this bit is ignored if master-slave manual config is disabled (register 9.12 = 0). rw 0 9.10 port type 1 = indicate the preference to operate as multiport device (master) 0 = indicate the preference to operate as single- port device ( slave ) this bit is valid only if the master-slave manual config enable bit is disabled (register 9.12 = 0). rw 0 9.9 1000base-t full-duplex 1 = advertise phy is 1000base-t full-duplex capable 0 = advertise phy is not 1000base-t full- duplex capable rw 1 9.8 1000base-t half-duplex 1 = advertise phy is 1000base-t half-duplex capable 0 = advertise phy is not 1000base-t half- duplex capable rw hardware setting 9.7:0 reserved write as 0, ignore on read ro register 10 (ah) ? 1000base-t status 10.15 master- slave configuration fault 1 = master-slave configuration fault detected 0 = no master-slave configuration fault detected ro/lh/sc 0
micrel, inc. ksz9021rl/rn october 2009 40 m9999-101309-1.1 address name description mode (1) default 10.14 master- slave configuration resolution 1 = local phy configuration resolved to master 0 = local phy configuration resolved to slave ro 0 10.13 local receiver status 1 = local receiver ok (loc_rcvr_status = 1) 0 = local receiver not ok (loc_rcvr_status = 0) ro 0 10.12 remote receiver status 1 = remote receiver ok (rem_rcvr_status = 1) 0 = remote receiver not ok (rem_rcvr_status = 0) ro 0 10.11 lp 1000t fd 1 = link partner is capable of 1000base-t full- duplex 0 = link partner is not capable of 1000base-t full-duplex ro 0 a.10 lp 1000t hd 1 = link partner is capable of 1000base-t half- duplex 0 = link partner is not capable of 1000base-t half-duplex ro 0 10.9:8 reserved ro 00 10.7:0 idle error count cumulative count of errors detected when receiver is receiving idles and pma_txmode.indicate = send_n. the counter is incremented every symbol period that rxerror_ status = error. ro/sc 0000_0000 register 11 (bh) ? extended register ? control 11.15 extended register ? read/write select 1 = write extended register 0 = read extended register rw 0 11.14:9 reserved rw 000_000 11.8 extended register ? page select page for extended register rw 0 11.7:0 extended register ? address select extended register address rw 0000_0000 register 12 (ch) ? extended register ? data write 12.15:0 extended register ? write 16-bit value to write to extend register address in register 11 (bh) bits [7:0] rw 0000_0000_0000_0000 register 13 (dh) ? extended register ? data read 13.15:0 extended register ? read 16-bit value read from extend register address in register 11 (bh) bits [7:0] ro 0000_0000_0000_0000 register 15 (fh) ? extended ? mii status 15.15 1000base-x full-duplex 1 = phy able to perform 1000base-x full-duplex 0 = phy not able to perform 1000base-x full-duplex ro 0
micrel, inc. ksz9021rl/rn october 2009 41 m9999-101309-1.1 address name description mode (1) default 15.14 1000base-x half-duplex 1 = phy able to perform 1000base-x half-duplex 0 = phy not able to perform 1000base-x half-duplex ro 0 15.13 1000base-t full-duplex 1 = phy able to perform 1000base-t full-duplex 1000base-x 0 = phy not able to perform 1000base-t full-duplex ro 1 15.12 1000base-t half-duplex 1 = phy able to perform 1000base-t half-duplex 0 = phy not able to perform 1000base-t half-duplex ro 1 15.11:0 reserved ignore when read ro - note: 1. rw = read/write. ro = read only. sc = self-cleared. lh = latch high. ll = latch low. vendor specific registers address name description mode (1) default register 17 (11h) ? remote loopback, led mode 17.15:9 reserved rw 0000_001 17.8 remote loopback 1 = enable remote loopback 0 = disable remote loopback rw 0 17.7:6 reserved rw 11 17.5:4 reserved rw 11 17.3 led test enable 1 = enable led test mode 0 = disable led test mode rw 0 17.2:1 reserved rw 00 17.0 reserved ro 0 register 18 (12h) ? linkmd ? ? cable diagnostic 18.15 reserved rw/sc 0 18.14:8 reserved rw 000_0000 18.7:0 reserved ro 0000_0000 register 19 (13h) ? digital pma/pcs status 19.15:3 reserved ro/lh 0000_0000_0000_0 19.2 1000base-t link status 1000 base-t link status 1 = link status is ok 0 = link status is not ok ro 0
micrel, inc. ksz9021rl/rn october 2009 42 m9999-101309-1.1 address name description mode (1) default 19.1 100base-tx link status 100 base-tx link status 1 = link status is ok 0 = link status is not ok ro 0 19.0 reserved ro 0 register 21 (15h) ? rxer counter 21.15:0 rxer counter receive error counter for symbol error frames ro/rc 0000_0000_0000_0000 register 27 (1bh) ? interrupt control/status 27.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 27.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 27.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 27.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 27.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 27.10 link down interrupt enable 1 = enable link down interrupt 0 = disable link down interrupt rw 0 27.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 27.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 27.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/rc 0 27.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/rc 0 27.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occurred ro/rc 0 27.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occurred ro/rc 0 27.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occurred ro/rc 0 27.2 link down interrupt 1 = link down occurred 0 = link down did not occurred ro/rc 0 27.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occurred ro/rc 0
micrel, inc. ksz9021rl/rn october 2009 43 m9999-101309-1.1 address name description mode (1) default 27.0 link up interrupt 1 = link up occurred 0 = link up did not occurred ro/rc 0 register 28 (1ch) ? digital debug control 1 28.15:8 reserved rw 0000_0000 28.7 mdi_set mdi_set has no function when swapoff (reg28.6) is de-asserted. 1 = when swapoff is asserted, if mdi_set is asserted, chip will operate at mdi mode. 0 = when swapoff is asserted, if mdi_set is de- asserted, chip will operate at mdi-x mode. rw 0 28.6 swapoff 1 = disable auto crossover function 0 = enable auto crossover function rw 0 28.5:1 reserved rw 00_000 28.0 pcs loopback 1 = enable 10base-t and 100base-tx loopback for register 0h bit 14. 0 = normal function rw 0 register 31 (1fh) ? phy control 31.15 reserved rw 0 31.14 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 31.13:12 reserved rw 00 31.11:10 reserved ro/lh/rc 00 31.9 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 31.8:7 reserved rw 00 31.6 speed status 1000base-t 1 = indicate chip final speed status at 1000base-t ro 0 31.5 speed status 100base-tx 1 = indicate chip final speed status at 100base-tx ro 0 31.4 speed status 10base-t 1 = indicate chip final speed status at 10base-t ro 0 31.3 duplex status indica te chip duplex status 1 = full-duplex 0 = half-duplex ro 0 31.2 1000base-t mater/slave status 1 = indicate 1000base-t master mode 0 = indicate 1000base-t slave mode ro 0 31.1 software reset 1 = reset chip, except all registers 0 = disable reset rw 0 31.0 link status check fail 1 = fail 0 = not failing ro 0 note: 1. rw = read/write. rc = read-cleared ro = read only. sc = self-cleared. lh = latch high.
micrel, inc. ksz9021rl/rn october 2009 44 m9999-101309-1.1 extended registers address name description mode (1) default register 256 (100h) ? common control 256.15:9 reserved rw 0000_000 256.8 rgmii in-band phy status 1 = enable 0 = disable rw 0 256.7:0 reserved rw register 257 (101h) ? strap status 257.15:6 reserved ro 257.5 clk125_en status 1 = clk125_en strap-in is enabled 0 = clk125_en strap-in is disabled ro 257.4:0 phyad[4:0] status strapped-in value for phy address ro register 258 (102h) ? operation mode strap override 258.15 rgmii all capabilities override 1 = override strap-in for rgmii advertise all capabilities rw 258.14 rgmii no 1000bt_hd override 1 = override strap-in for rgmii advertise all capabilities except 1000base-t half-duplex rw 258.13 rgmii 1000bt_h/fd only override 1 = override strap-in for rgmii advertise 1000base-t full and half-duplex only rw 258.12 rgmii 1000bt_fd only override 1 = override strap-in for rgmii advertise 1000base-t full-duplex only rw 258.11:8 reserved rw 258.7 tri-state all digital i/os 1 = tri-state all digital i/os for further power saving during software power down rw 0 258.6:5 reserved rw 258.4 nand tree override 1 = override strap-in for nand tree mode rw 258.3:0 reserved rw register 259 (103h) ? operation mode strap status 259.15 rgmii all capabilities strap-in status 1 = strap to rgmii advertise all capabilities ro 259.14 rgmii no 1000bt_hd strap-in status 1 = strap to rgmii advertise all capabilities except 1000base-t half-duplex ro 259.13 rgmii only 1000bt_h/fd strap-in status 1 = strap to rgmii advertise 1000base-t full and half-duplex only ro 259.12 rgmii only 1000bt_fd strap-in status 1 = strap to rgmii advertise 1000base-t full- duplex only ro 259.11:5 reserved ro
micrel, inc. ksz9021rl/rn october 2009 45 m9999-101309-1.1 address name description mode (1) default 259.4 nand tree strap-in status 1 = strap to nand tree mode ro 259.3:0 reserved ro register 260 (104h) ? rgmii clock and control pad skew 260.15:12 rxc _pad_skew rgmii rxc pad skew control (0.2ns/step) rw 0111 260.11:8 rxdv _pad_skew rgmii rx_ctl pad skew control (0.2ns/step) rw 0111 260.7:4 txc _pad_skew rgmii txc pad skew control (0.2ns/step) rw 0111 260.3:0 tx en_pad_skew rgmii tx_ctl pad skew control (0.2ns/step) rw 0111 register 261 (105h) ? rgmii rx data pad skew 261.15:12 rx d3_pad_skew rgmii rxd3 pad skew control (0.2ns/step) rw 0111 261.11:8 rx d2_pad_skew rgmii rxd2 pad skew control (0.2ns/step) rw 0111 261.7:4 rx d1_pad_skew rgmii rxd1 pad skew control (0.2ns/step) rw 0111 261.3:0 rx d0_pad_skew rgmii rxd0 pad skew control (0.2ns/step) rw 0111 register 263 (107h) ? analog test register 263.15 ldo disable 1 = ldo controller disable 0 = ldo controller enable rw 0 263.14:9 reserved rw 000_000 263.8 low frequency oscillator mode 1 = low frequency oscillator mode enable 0 = low frequency oscillator mode disable use for further power saving during software power down. rw 0 263.7:0 reserved rw 0000_0000 note: 1. rw = read/write. ro = read only.
micrel, inc. ksz9021rl/rn october 2009 46 m9999-101309-1.1 absolute maximum ratings (1) supply voltage (dvddl, avddl, avddl_pll)....... -0.5v to v dd +10% (avddh).......................................... -0.5v to v dd +10% (dvddh)................................ -0.5v to v dd (3.3v)+10% input voltage (all i nputs) ........................ -0.5v to v dd +10% output voltage (all outputs) ................... -0.5v to v dd +10% lead temperature (solde ring, 10sec .)....................... 260c storage temperature (t s ) ..........................-55c to +150c operating ratings (2) supply voltage (dvddl, avddl, avddl_pll).... +1.140v to +1.260v (avddh)........................................ +3.135v to +3.465v (dvddh @ 3.3v) .......................... +3.135v to +3.465v (dvddh @ 2.5v) .......................... +2.375v to +2.625v ambient temperature (t a commercial: ksz9021rl/rn) .......... 0c to +70c (t a industrial: ksz9021rli/rni) ..........-40c to +85c maximum junction temperature (t j max) ................. 125c thermal resistance ( ja ) ....................................31.85c/w thermal resistance ( jc ) ......................................8.07c/w electrical characteristics (3) symbol parameter condition min typ max units supply current ? core / digital i/os 1000base-t link-up (no traffic) 528 ma 1000base-t full-duplex @ 100% utilization 563 ma 100base-tx link-up (no traffic) 158 ma 100base-tx full-duplex @ 100% utilization 158 ma 10base-t link-up (no traffic) 7 ma 10base-t full-duplex @ 100% utilization 7 ma power saving mode (cable unplugged) 15 ma software power down mode (register 0.11 =1) 1.3 ma i core 1.2v total of: dvddl (1.2v digital core) + avddl (1.2v analog core) + avddl_pll (1.2v for pll) chip power down mode (strap-in pins mode[3:0] = 0111) 1.3 ma 1000base-t link-up (no traffic) 13 ma 1000base-t full-duplex @ 100% utilization 37 ma 100base-tx link-up (no traffic) 4 ma 100base-tx full-duplex @ 100% utilization 9 ma 10base-t link-up (no traffic) 2 ma 10base-t full-duplex @ 100% utilization 5 ma power saving mode (cable unplugged) 7 ma software power down mode (register 0.11 =1) 3 ma i dvddh_2.5 2.5v for digital i/os (rgmii operating @ 2.5v) chip power down mode (strap-in pins mode[3:0] = 0111) 1 ma 1000base-t link-up (no traffic) 20 ma 1000base-t full-duplex @ 100% utilization 58 ma 100base-tx link-up (no traffic) 11 ma 100base-tx full-duplex @ 100% utilization 15 ma 10base-t link-up (no traffic) 5 ma 10base-t full-duplex @ 100% utilization 11 ma power saving mode (cable unplugged) 9 ma software power down mode (register 0.11 =1) 7 ma i dvddh_3.3 3.3v for digital i/os (rgmii operating @ 3.3v) chip power down mode (strap-in pins mode[3:0] = 0111) 1 ma
micrel, inc. ksz9021rl/rn october 2009 47 m9999-101309-1.1 symbol parameter condition min typ max units supply current ? transceiver (equivalent to current draw through external transformer center taps for phy transceivers with current-mode transmit drivers) 1000base-t link-up (no traffic) 75 ma 1000base-t full-duplex @ 100% utilization 75 ma 100base-tx link-up (no traffic) 29 ma 100base-tx full-duplex @ 100% utilization 29 ma 10base-t link-up (no traffic) 35 ma 10base-t full-duplex @ 100% utilization 43 ma power saving mode (cable unplugged) 36 ma software power down mode (register 0.11 =1) 2 ma i avddh 3.3v for transceiver chip power down mode (strap-in pins mode[3:0] = 0111) 1 ma ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = gnd ~ v ddio -10 10 a ttl outputs v oh output high voltage i oh = -4ma 2.4 v v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri-state leakage 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % v set reference voltage of i set r(i set ) = 4.99k 0.535 v output jitter peak-to-peak 0.7 1.4 ns 10base-t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 ? termination across differential output 2.2 2.8 v jitter added peak-to-peak 3.5 ns harmonic rejection transmit all-one signal sequence -31 db 10base-t receive v sq squelch threshold 5mhz square wave 300 400 mv notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause pe rmanent damage to the device. operation of the device at these or an y other conditions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25 c. specification is for packaged product only.
micrel, inc. ksz9021rl/rn october 2009 48 m9999-101309-1.1 timing diagrams rgmii timing the ksz9021rl/rn rgmii timing conforms to the timing re quirements per the rgmii version 1.3 specification. figure 5. rgmii v1.3 specification (fig ure 2 ? multiplexing and timing diagram) timing parameter description min typ max unit tskewt data to clock output skew (at transmitter) -500 500 ps tskewr data to clock input skew (at receiver) 1 2.6 ns tcyc (1000base-t) clock cycle duration for 1000base-t 7.2 8 8.8 ns tcyc (100base-tx) clock cycle duration for 100base-tx 36 40 44 ns tcyc (10base-t) clock cycle duration for 10base-t 360 400 440 ns table 10. rgmii v1.3 specification (timing specifics from table 2) accounting for tskewt, the tskewr specif ication in the above table requires t he pcb board design to incorporate clock routing for txc and rxc with an additional trace delay of greater than 1.5ns and less than 2.1ns for 1000base-t. for 10base-t/100base-tx, the maximum delay is much greater t han the 2.1ns for 1000base-t, and thus is not specified.
micrel, inc. ksz9021rl/rn october 2009 49 m9999-101309-1.1 auto-negotiation timing auto-negotiation fast link pulse (flp) timing t pw tx+/tx- clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx+/tx- data pulse flp burst flp burst figure 6. auto-negotiation fast link pulse (flp) timing timing parameter description min typ max units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 table 11. auto-negotiation fast link pulse (flp) timing parameters
micrel, inc. ksz9021rl/rn october 2009 50 m9999-101309-1.1 mdc/mdio timing t md1 valid data mdio (phy input) valid data mdc t md2 mdio (phy output) valid data t md3 t p figure 7. mdc/mdio timing timing parameter description min typ max unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 10 ns t md3 mdio (phy output) delay from rising edge of mdc 0 ns table 12. mdc/mdio timing parameters
micrel, inc. ksz9021rl/rn october 2009 51 m9999-101309-1.1 reset timing the recommended ksz9021rl/rn power-up reset timing is summarized in the following figure and table. tsr supply voltage reset_n figure 8. reset timing parameter description min max units t sr stable supply voltage to reset high 10 ms table 13. reset timing parameters after the de-assertion of reset, it is recommended to wait a minimum of 100s before st arting programming on the miim (mdc/mdio) interface. reset circuit the following reset circuit is recommended for powering up t he ksz9021rl/rn if reset is triggered by the power supply. ksz9021rl/rn 3.3v d1 d1: 1n4148 r 10k c 10uf reset_n figure 9. recommended reset circuit
micrel, inc. ksz9021rl/rn october 2009 52 m9999-101309-1.1 the following reset circuit is recommended for applications w here reset is driven by another device (e.g., cpu or fpga). at power-on-reset, r, c and d1 provi de the necessary ramp rise time to reset the ksz9021rl/rn device. the rst_out_n from cpu/fpga provides the warm reset after power up. ksz9021rl/rn cpu/fpga 3.3v c 10uf r 10k rst_out_n d1 d2 d1, d2: 1n4148 reset_n figure 10. recommended reset circuit for interfacing with cpu/fpga reset output reference circuits ? led strap-in pins the pull-up and pull-down reference circuits for the le d2/phyad1 and led1/phyad0 stra pping pins are shown in the following figure. figure 11. reference circuits for led strapping pins
micrel, inc. ksz9021rl/rn october 2009 53 m9999-101309-1.1 reference clock ? conn ection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the ksz9021rl/rn. the reference clock is 25 mhz for all operating modes of the ksz9021rl/rn. the following figure and table shows the reference clock conn ection to pins xi and xo of the ksz9021rl/rn, and the reference clock selection criteria. 25mhz osc +/-50ppm nc nc xi xo xi xo 22pf 22pf 22pf 22pf 25mhz xtal +/-50ppm figure 12. 25mhz crystal / oscillator reference clock connection characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm table 14. reference crystal/clock selection criteria magnetics specification a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode chokes is recommended for exceeding fcc requirements. the following tables provide recommended magnetic char acteristics and a list of qualified magnetics for the ksz9021rl/rn. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (max.) 1.0db 0mhz ? 100mhz hipot (min.) 1500vrms table 15. magnetics selection criteria magnetic manufacturer part number auto mdi-x number of port pulse h5007nl yes 1 tdk tla-7t101lf yes 1 table 16. qualified single port 10/100/1000 magnetics
micrel, inc. ksz9021rl/rn october 2009 54 m9999-101309-1.1 package information 48-pin (7mm x 7mm) qfn
micrel, inc. ksz9021rl/rn october 2009 55 m9999-101309-1.1 64-pin (10mm x 10mm) e-lqfp (v)
micrel, inc. ksz9021rl/rn october 2009 56 m9999-101309-1.1 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as co mponents in life support appliances, devices or systems where malfunction of a product can reasonably be expected to resu lt in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical im plant into the body or (b) supp ort or sustain life, and whose failure to perform can be reasonably expected to result in a si gnificant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s ow n risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2009 micrel, incorporated.

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